說明
These octal buffers and line drivers are designed specifically to improve both the performance and density of three-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The designer has a choice of selected combinations of inverting and noninverting outputs, symmetrical, active-low output-control (G)\ inputs, and complementary output-control (G and G\) inputs. These devices feature high fan-out, improved fan-in, and 400-mV noise margin. The SN74LS’ and SN74S’ devices can be used to drive terminated lines down to 133 
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